Optimization of DML Gates

Itamar Levi; Alexander Fish

doi:10.1007/978-3-030-40786-5_3

Optimization of DML Gates

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

This chapter presents several techniques to achieve high-performance and/or low-energy operation of DML circuits. We introduce several optimization methodologies for DML circuits while focusing on gate-level techniques. This goal is primarily achieved by utilizing...

Original language	English
Title of host publication	Dual Mode Logic
Place of Publication	Cham, Switzerland
Publisher	Springer
Pages	35-57
Number of pages	23
DOIs	https://doi.org/10.1007/978-3-030-40786-5_3
State	Published - 16 Dec 2020

Keywords

Logical effort (LE)
CMOS-LE
DML-LE
Inverter chain
Sizing optimization
Sizing factors
Complete un-approximated method (CS)
Complete approximated method (CA)
Fan-out
Semi-approximated method (SA)
Electrical effort
Branching effort
Delay error
DML

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10.1007/978-3-030-40786-5_3

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KW - Inverter chain

KW - Sizing optimization

KW - Sizing factors

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KW - Complete approximated method (CA)

KW - Fan-out

KW - Semi-approximated method (SA)

KW - Electrical effort

KW - Branching effort

KW - Delay error

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Optimization of DML Gates

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Keywords

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