Optimization of a back bias generator for NMOS VLSI

T. Liran

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An optimized back bias generator (BBG) was designed and implemented in the NS32332 32-bit microprocessor. A novel analysis method based on energy transfer in the charge pump circuit was used for better understanding of the circuit. The complete considerations, implementation, and the improved performance results are presented and discussed. The most important design consideration was to implement a very strong pump and to eliminate mechanisms that might cause instabilities. It has been shown that even a relatively small BBG can pump a large VLSI NMOS circuit to a stable predetermined voltage.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages1601-1606
Number of pages6
ISBN (Print)9517212402
StatePublished - 1988
Externally publishedYes

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2
ISSN (Print)0271-4310

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