Abstract
Some apparently different VLSI circuit design optimization problems can be mapped to the problem of allocating weights (hardware circuits) to the nodes of a tree, such that their total sum (delay) along root-to-leaf paths, or their total product (amplification) along root-to-leaf paths, satisfy given demands (delays or amplifications, respectively) at the tree’s leaves. Node’s weight is shared by all the leaves of its emanating sub-tree. For both the sum and product constraints cases, (Formula presented.) weights allocation algorithms are presented, supplying the demands at the leaves, while the total sum of nodes’ weights (hardware cost) is minimized. When the assignment of the demands to leaves is not predetermined, it is shown that monotonic order of the demands at leaves is optimal for both cases.
Original language | English |
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Pages (from-to) | 1023-1033 |
Number of pages | 11 |
Journal | Journal of Combinatorial Optimization |
Volume | 31 |
Issue number | 3 |
DOIs | |
State | Published - 1 Apr 2016 |
Bibliographical note
Publisher Copyright:© 2014, Springer Science+Business Media New York.
Keywords
- Amplifier-tree
- Binary tree optimization
- Clock-tree
- Weight allocation