Interconnect shielding is used in VLSI designs to avoid noise interference from the cross-coupling capacitance between adjacent signals. This paper takes advantage of the shields already present in the design and uses them to tune the propagation delay of the clock signals, thus eliminating expensive dedicated delay buffers. The problem of obtaining the desired delay at a minimum shielding cost (silicon area) is formulated as a calculus of variations problem. An analytical solution shows that a square root shield profile is optimal.
|Number of pages||8|
|Journal||Journal of Optimization Theory and Applications|
|State||Published - 1 Sep 2016|
Bibliographical noteFunding Information:
The authors are thankful for the useful comments and corrections made by the editor Prof. D. Hull. This research was supported by the Office of the Israeli Chief Scientist under the HiPer consortium of the MAGNET program.
© 2016, Springer Science+Business Media New York.
- Calculus of variations
- Delay tuning
- Wire shielding