Optimal resizing of bus wires in layout migration

Shay Michaely, Shmuel Wimer, Avinoam Kolodny

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of processing technology, because wire resistance and cross capacitances become more important with scaling. In this paper, timing optimization of signal busses is performed by resizing and spacing individual bus wires, while the total area of the whole bus structure is regarded as a fixed constraint Properties of optimal bus layouts are proven, and an iterative algorithm to find the optimal wire widths and spaces is presented. Examples of solutions are shown. Guidelines for design are derived from these results. © 2004 IEEE.
Original languageEnglish
Journal11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004
StatePublished - 1 Dec 2004


Dive into the research topics of 'Optimal resizing of bus wires in layout migration'. Together they form a unique fingerprint.

Cite this