Abstract
The embedded memories of ultra-low power processors require periodic refreshing, which blocks the CPU-memory access and degrades performance. In addition, refreshing queues cause a drop in system performance not only when they are saturated but also when they are empty. We present an optimal queuing-based opportunistic refreshing algorithm that eliminates performance loss. We analyze system performance dependence on queue capacity and memory size to derive a closed-form performance expression that provides clear guidelines for memory design implementation. Comparison of a hardware implementation in a RISC-V ultra-low power processor to ordinary periodic refreshing demonstrates the algorithm can provide a considerable performance speedup in a wide variety of real applications.
Original language | English |
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Pages (from-to) | 505-514 |
Number of pages | 10 |
Journal | Computers and Electrical Engineering |
Volume | 71 |
DOIs | |
State | Published - Oct 2018 |
Bibliographical note
Publisher Copyright:© 2018 Elsevier Ltd
Funding
This work was supported by the Israel Innovation Authority (MAGNET program) under the HiPer consortium. The authors are grateful to Prof. L. Benini of ETHZ and Prof. D. Rossi of the University of Bologna and their team for making available and supporting the PULPino design. We acknowledge the useful comments by the anonymous reviewers who enabled us to improve the manuscript.
Funders | Funder number |
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Israel Innovation Authority |
Keywords
- Embedded memories
- Finite capacity queue
- Queuing
- Refreshing