TY - JOUR
T1 - OPTIMAL CHAINING OF CMOS TRANSISTORS IN A FUNCTIONAL CELL.
AU - Wimer, Shmuel
AU - Pinter, Ron Y.
AU - Feldman, Jack A.
PY - 1986/9
Y1 - 1986/9
N2 - An algorithm that maps a CMOS circuit diagram into an area-efficient, high-performance layout in the style of a transistor chain is described. It is superior to other published algorithms of this kind in terms of the class of input circuits it accepts, its efficiency, and the quality of the results it produces. This algorithm is intended for the automatic generation of basic cells in a custom or semicustom design environment, thereby removing the burden of arduous mask definition from the designer. It is shown how the method was used to compose cells in a row into a functional slice (e. g. , an adder) that can be used in, e. g. , a data path.
AB - An algorithm that maps a CMOS circuit diagram into an area-efficient, high-performance layout in the style of a transistor chain is described. It is superior to other published algorithms of this kind in terms of the class of input circuits it accepts, its efficiency, and the quality of the results it produces. This algorithm is intended for the automatic generation of basic cells in a custom or semicustom design environment, thereby removing the burden of arduous mask definition from the designer. It is shown how the method was used to compose cells in a row into a functional slice (e. g. , an adder) that can be used in, e. g. , a data path.
UR - http://www.scopus.com/inward/record.url?scp=0022781763&partnerID=8YFLogxK
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AN - SCOPUS:0022781763
SN - 0278-0070
VL - CAD-6
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 5
ER -