Optimal Chaining of CMOS Transistors in a Functional Cell

Shmuel Wimer, Ron Y. Pinter, Jack A. Feldman

Research output: Contribution to journalArticlepeer-review

45 Scopus citations


We describe an algorithm that maps a CMOS circuit diagram into an area-efficient, high-performance layout in the style of a transistor chain. It is superior to other published algorithms of this kind in terms of the class of input circuits it accepts, its efficiency, and the quality of the results it produces. This algorithm is intended for the automatic generation of basic cells in a custom or semicustom design environment, thereby removing the burden of arduous mask definition from the designer. We show how our method was used to compose cells in a row into a functional slice (e.g. an adder) that can be used in, say, a data path.

Original languageEnglish
Pages (from-to)795-801
Number of pages7
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number5
StatePublished - Sep 1987
Externally publishedYes


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