Abstract
Embedded DRAM (eDRAM) is an alternative technology that can replace the area and power consumed by SRAM cache memories. eDRAM consumes half the area and an order of magnitude less power than SRAM, but has the drawback of access blockage caused by its periodic data refreshing. This paper presents an opportunistic refreshing algorithm along with the appropriate memory architecture and skim control logic. This architecture takes advantage of the access idleness of the internal partitions of the memory and enables most of the refreshing operations to run concurrently with the ordinary R/W access. This eliminates the refreshing burden almost completely. The algorithm was simulated with industrial DSP access traces, and outperformed in a wide range of eDRAM technologies and internal memory architectures.
| Original language | English |
|---|---|
| Article number | 7571130 |
| Pages (from-to) | 1921-1932 |
| Number of pages | 12 |
| Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
| Volume | 63 |
| Issue number | 11 |
| DOIs | |
| State | Published - Nov 2016 |
Bibliographical note
Publisher Copyright:© 2004-2012 IEEE.
Funding
Manuscript received May 7, 2016; revised June 25, 2016 and July 25, 2016; accepted August 11, 2016. Date of publication September 19, 2016; date of current version October 25, 2016. This work was supported by the Israeli Chief Scientist under the HiPer consortium of the MAGNET program. This paper was recommended by Associate Editor Y. Pu.
| Funders | Funder number |
|---|---|
| Israeli Chief Scientist |
Keywords
- L1 cache
- eDRAM
- low-power cache
- refreshing algorithms
- refreshing control