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On optimal ordering of signals in parallel wire bundles
Konstantin Moiseev
,
Shmuel Wimer
, Avinoam Kolodny
Technion-Israel Institute of Technology
Intel
Research output
:
Contribution to journal
›
Article
›
peer-review
7
Scopus citations
Overview
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Keyphrases
Optimal Order
100%
Parallel Wire
100%
Average Delay
100%
Wire Bundles
100%
Technology Design
50%
Near-optimal
50%
Design Information
50%
Miller
50%
Min-max
50%
Wire Delay
50%
Wire Width
50%
65 Nm Technology
50%
Delay Optimization
50%
Process Technology
50%
Numerical Experiments
50%
Industrial Design
50%
Ordering Property
50%
VLSI Circuits
50%
Common Design
50%
Design Practice
50%
High Performance Microprocessor
50%
Optimal Sizing
50%
Coupling Factor
50%
Engineering
Interconnects
100%
Microprocessor Chips
100%
Internals
100%
VLSI Circuits
100%
Numerical Experiment
100%
Broad Range
100%
Product Design
100%
Design Data
100%
Optimal Setting
100%
Clock Cycle
100%
Good Approximation
100%
Computer Science
Weighted Average
100%
Clock Cycle
33%
Design Practice
33%
High-Performance Microprocessor
33%
Good Approximation
33%
Optimal Setting
33%
Mathematics
Weighted Average
100%
Numerical Experiment
33%
Good Approximation
33%
Economics, Econometrics and Finance
Product Design
100%