Offset-compensated switched-capacitor delay circuit that is insensitive to stray capacitance and to capacitor mismatch

A switched-capacitor delay circuit that is offset-compensated and insensitive to stray capacitance and to capacitor mismatch is proposed. It uses a four-phase clock and contains a single operational amplifier, two capacitors and seven switches. A delay line composed of such building blocks requires only two operational amplifiers per three delay sections and two clock phases per sample.