Non-Volatile Content-Addressable Memory for Energy-Efficient & High-Performance Search and Update Operations

Alessandro Bedoya; Benjamin Zambrano; Ramiro Taco; Luis Miguel Prócel; Marco Lanuzza; Esteban Garzón

doi:10.1109/ISCAS56072.2025.11044106

Non-Volatile Content-Addressable Memory for Energy-Efficient & High-Performance Search and Update Operations

Alessandro Bedoya
, Benjamin Zambrano
, Ramiro Taco
, Luis Miguel Prócel
, Marco Lanuzza
, Esteban Garzón

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This work presents a non-volatile content-addressable memory (NV-CAM) based on double-barrier magnetic tunnel junction technology (DMTJ). Unlike state-of-the-art NV-CAM designs that present low-performance updates, our NV-CAM allows energy-efficient, high-performance search and update operations. This makes it well-suited for applications requiring a high frequency of searches/updates, such as associative processors. The NV-CAM hybrid CMOS/DMTJ was designed using a commercial 65nm CMOS technology and a Verilog-A-based DMTJ compact model. The NV-CAM evaluation was carried out by employing Monte Carlo simulations while accounting for process variations. Simulation results show that our NV-CAM presents competitive figures of merit compared to state-of-the-art design. Our NV-CAM presents energy-efficient operations and reduces the update and search delay by about 71% and 75%, respectively, compared to other NV-CAMs.

Original language	English
Title of host publication	ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350356830
DOIs	https://doi.org/10.1109/ISCAS56072.2025.11044106
State	Published - 2025
Externally published	Yes
Event	2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 - London, United Kingdom Duration: 25 May 2025 → 28 May 2025

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
Country/Territory	United Kingdom
City	London
Period	25/05/25 → 28/05/25

Bibliographical note

Publisher Copyright:
© 2025 IEEE.

Keywords

CAM
Content-addressable memory
DMTJ
Non-Volatile CAM
double-barrier magnetic tunnel junction

Access to Document

10.1109/ISCAS56072.2025.11044106

Cite this

Bedoya, A., Zambrano, B., Taco, R., Prócel, L. M., Lanuzza, M., & Garzón, E. (2025). Non-Volatile Content-Addressable Memory for Energy-Efficient & High-Performance Search and Update Operations. In ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS56072.2025.11044106

Bedoya, Alessandro ; Zambrano, Benjamin ; Taco, Ramiro et al. / Non-Volatile Content-Addressable Memory for Energy-Efficient & High-Performance Search and Update Operations. ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2025. (Proceedings - IEEE International Symposium on Circuits and Systems).

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title = "Non-Volatile Content-Addressable Memory for Energy-Efficient \& High-Performance Search and Update Operations",

abstract = "This work presents a non-volatile content-addressable memory (NV-CAM) based on double-barrier magnetic tunnel junction technology (DMTJ). Unlike state-of-the-art NV-CAM designs that present low-performance updates, our NV-CAM allows energy-efficient, high-performance search and update operations. This makes it well-suited for applications requiring a high frequency of searches/updates, such as associative processors. The NV-CAM hybrid CMOS/DMTJ was designed using a commercial 65nm CMOS technology and a Verilog-A-based DMTJ compact model. The NV-CAM evaluation was carried out by employing Monte Carlo simulations while accounting for process variations. Simulation results show that our NV-CAM presents competitive figures of merit compared to state-of-the-art design. Our NV-CAM presents energy-efficient operations and reduces the update and search delay by about 71\% and 75\%, respectively, compared to other NV-CAMs.",

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author = "Alessandro Bedoya and Benjamin Zambrano and Ramiro Taco and Pr{\'o}cel, \{Luis Miguel\} and Marco Lanuzza and Esteban Garz{\'o}n",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 ; Conference date: 25-05-2025 Through 28-05-2025",

year = "2025",

doi = "10.1109/ISCAS56072.2025.11044106",

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Bedoya, A, Zambrano, B, Taco, R, Prócel, LM, Lanuzza, M & Garzón, E 2025, Non-Volatile Content-Addressable Memory for Energy-Efficient & High-Performance Search and Update Operations. in ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025, London, United Kingdom, 25/05/25. https://doi.org/10.1109/ISCAS56072.2025.11044106

Non-Volatile Content-Addressable Memory for Energy-Efficient & High-Performance Search and Update Operations. / Bedoya, Alessandro; Zambrano, Benjamin; Taco, Ramiro et al.
ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2025. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Bedoya, Alessandro

AU - Zambrano, Benjamin

AU - Taco, Ramiro

AU - Prócel, Luis Miguel

AU - Lanuzza, Marco

AU - Garzón, Esteban

PY - 2025

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N2 - This work presents a non-volatile content-addressable memory (NV-CAM) based on double-barrier magnetic tunnel junction technology (DMTJ). Unlike state-of-the-art NV-CAM designs that present low-performance updates, our NV-CAM allows energy-efficient, high-performance search and update operations. This makes it well-suited for applications requiring a high frequency of searches/updates, such as associative processors. The NV-CAM hybrid CMOS/DMTJ was designed using a commercial 65nm CMOS technology and a Verilog-A-based DMTJ compact model. The NV-CAM evaluation was carried out by employing Monte Carlo simulations while accounting for process variations. Simulation results show that our NV-CAM presents competitive figures of merit compared to state-of-the-art design. Our NV-CAM presents energy-efficient operations and reduces the update and search delay by about 71% and 75%, respectively, compared to other NV-CAMs.

AB - This work presents a non-volatile content-addressable memory (NV-CAM) based on double-barrier magnetic tunnel junction technology (DMTJ). Unlike state-of-the-art NV-CAM designs that present low-performance updates, our NV-CAM allows energy-efficient, high-performance search and update operations. This makes it well-suited for applications requiring a high frequency of searches/updates, such as associative processors. The NV-CAM hybrid CMOS/DMTJ was designed using a commercial 65nm CMOS technology and a Verilog-A-based DMTJ compact model. The NV-CAM evaluation was carried out by employing Monte Carlo simulations while accounting for process variations. Simulation results show that our NV-CAM presents competitive figures of merit compared to state-of-the-art design. Our NV-CAM presents energy-efficient operations and reduces the update and search delay by about 71% and 75%, respectively, compared to other NV-CAMs.

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ER -

Bedoya A, Zambrano B, Taco R, Prócel LM, Lanuzza M, Garzón E. Non-Volatile Content-Addressable Memory for Energy-Efficient & High-Performance Search and Update Operations. In ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2025. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS56072.2025.11044106

Non-Volatile Content-Addressable Memory for Energy-Efficient & High-Performance Search and Update Operations

Abstract

Publication series

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Bibliographical note

Keywords

Access to Document

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