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Non-redundant Scheme for Arbitrary Error Detection in Combinational Circuits

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Abstract

The paper deals with synthesis technique for designing circuits with on-line errors detection. We present a new technique of designing a concurrently checking functional circuit by partitioning the circuit into two independent sub-circuits. The technique does not require any redundant coding variables. Instead, we propose to utilize some input variables. These variables are transferred directly into the checker providing the self-checking property for arbitrary errors (not necessarily unidirectional). A method for constructing the overall system is presented. Benchmark results are presented and show the efficiency of the proposed approach
Original languageAmerican English
Title of host publicationIFIP/IEEE VLSI-SoC - International Conference on Very Large Scale Integration
StatePublished - 2008

Bibliographical note

Place of conference:Greece

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