TY - GEN
T1 - Next generation RadSafe™ technology for SoCs
AU - Liran, Tuvia
AU - Ginosar, Ran
AU - Alon, Dov
AU - Dobkin, Reuven
AU - Goldberg, Michael
PY - 2012
Y1 - 2012
N2 - The next generation RadSafe™ technology is dedicated to advance System on Chip (SoC) devices for space applications of digital signal processing and micro-processors. The technology should maximize processing performance by combining advanced micro-architecture, advanced silicon technology and high speed interfacing to peripheral devices. However, the requirements for very high reliability, cost and availability limit the use of the most advanced technologies. For the next generation RadSafe™ technology we selected the 0.13μm technology. It provides significant improvement of performance and power, while this technology is mature, and available for affordable price. The improved design infrastructure includes improvements of the standard cells, I/O cells, SRAMs and DLLs. The new cores include high speed SERDES and DDR I/F. An improved packaging technology, name RCpack™, is introduced. It provides improved pin count and signal integrity while complying with space requirements. The new capabilities will enable the implementation of space grade RC64 - a many-core processor that will provide ∼10G instructions per second [2], mostly for high performance signal processing.
AB - The next generation RadSafe™ technology is dedicated to advance System on Chip (SoC) devices for space applications of digital signal processing and micro-processors. The technology should maximize processing performance by combining advanced micro-architecture, advanced silicon technology and high speed interfacing to peripheral devices. However, the requirements for very high reliability, cost and availability limit the use of the most advanced technologies. For the next generation RadSafe™ technology we selected the 0.13μm technology. It provides significant improvement of performance and power, while this technology is mature, and available for affordable price. The improved design infrastructure includes improvements of the standard cells, I/O cells, SRAMs and DLLs. The new cores include high speed SERDES and DDR I/F. An improved packaging technology, name RCpack™, is introduced. It provides improved pin count and signal integrity while complying with space requirements. The new capabilities will enable the implementation of space grade RC64 - a many-core processor that will provide ∼10G instructions per second [2], mostly for high performance signal processing.
UR - http://www.scopus.com/inward/record.url?scp=84870988909&partnerID=8YFLogxK
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AN - SCOPUS:84870988909
SN - 9789290922650
T3 - European Space Agency, (Special Publication) ESA SP
BT - Proceedings of DASIA 2012 - DAta Systems In Aerospace
T2 - DAta Systems In Aerospace, DASIA 2012
Y2 - 14 May 2012 through 16 May 2012
ER -