Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism †

Keyphrases

• Bitcell 100%
• Gain-cell Embedded DRAM (GC-eDRAM) 100%
• Gain Cell 75%
• Embedded Memory 50%
• System-on-chip 50%
• Transistor 25%
• Cell Design 25%
• Operation Mode 25%
• Limited Availability 25%
• Large Memory 25%
• High Power 25%
• EDRAM 25%
• Graphics Processing Unit 25%
• Modern Systems 25%
• FDSOI Technology 25%
• DRAM Memory 25%
• Refresh Operation 25%
• High Density 25%
• Dynamic Memory 25%
• Power Budget 25%
• Cell Memory 25%
• Hidden Refresh 25%
• Proposed Design 25%
• UTBB FD-SOI 25%
• Design Features 25%
• Read Port 25%
• Chip Processing 25%
• Four-port 25%
• Media Systems 25%
• Data-limited 25%

Engineering

• System-on-Chip 100%
• Cell Design 50%
• Design Feature 50%
• Processing Unit 50%
• Modern System 50%
• Power Budget 50%