Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism †

Roman Golman, Robert Giterman, Adam Teman

Research output: Contribution to journalArticlepeer-review

Abstract

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for multi-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel multi-ported gain-cell design, which provides up-to N read ports and M independent write ports (NRMW). In addition, the proposed design features a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability, as well as a novel opportunistic refresh port approach. An 8kbit memory macro was implemented using a four-transistor bitcell with four ports (2R2W) in a 28 nm FD-SOI technology, offering up-to a 3× reduction in bitcell area compared to other dual-ported SRAM memory options, while also providing 100% memory availability, as opposed to conventional dynamic memories, which are hindered by limited availability.

Original languageEnglish
Article number2
JournalJournal of Low Power Electronics and Applications
Volume14
Issue number1
DOIs
StatePublished - Mar 2024

Bibliographical note

Publisher Copyright:
© 2024 by the authors.

Keywords

  • 1R1W
  • 2R2W
  • 6R2W
  • GC-eDRAM
  • N-ported
  • configurable memory
  • dual-port
  • multi-port
  • refresh
  • two-port

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