Modular, Low-Cost Bus and ECC Encoders for Memory Macros Under Maximal Power Constraints

The power consumed when writing to some emerging memory arrays, such as certain varieties of Resistive Random Access Memory (RRAM), is significantly greater than that consumed by many charge-based memories such as SRAM. As a result, when used in applications where instantaneous power consumption is constrained, the number of bit transitions is limited. In this paper, we present modular, low cost, power-efficient differential bus encoders (DBEs) and (related) encoders for error correcting codes. Combining a DBE module and an encoder for a power-efficient single error correcting (PESEC) code ensures low-power operation and reliable data storage, and with a minor modification, a PESEC encoder becomes a PESEC+DED encoder. These encoders make use of systematic, multiple-representation based, error correcting codes. It is shown that when one of our DBEs is used with one of these PESEC encoders, the combined system requires about twenty-five percent fewer bit transitions and ten to twenty percent fewer redundant bits than similar techniques. Moreover, the addition of a PESEC encoder only causes a marginal change in implementation cost relative to that of an encoder for a standard Hamming code. Furthermore, the techniques proposed here do not require huge lookup tables, as do other power-aware techniques. Finally, our PESEC encoders can be used with any bus encoder.