Modular gm-C programmable CNN implementation

Drahoslav Lim; George S. Moschytz

Modular g_m-C programmable CNN implementation

Drahoslav Lim, George S. Moschytz

Swiss Federal Institute of Technology Zurich

Research output: Contribution to journal › Conference article › peer-review

6 Scopus citations

Abstract

A programmable cellular neural network has been designed in a 0.8 μ CMOS technology. An arbitrarily large analog CNN can be constructed by modularly connecting `tile' CNN chips, each with a modest number of cells. The network operates in continuous time, has a PWL output function, and the cell connections (template values) are realized as sets of switchable unit and half-unit transconductors. Matching accuracy, including matching among chips from different manufacturing runs, and operation was verified on uncoupled and coupled templates.

Original language	English
Pages (from-to)	139-142
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
State	Published - 1998
Externally published	Yes
Event	Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA Duration: 31 May 1998 → 3 Jun 1998

Cite this

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title = "Modular gm-C programmable CNN implementation",

abstract = "A programmable cellular neural network has been designed in a 0.8 μ CMOS technology. An arbitrarily large analog CNN can be constructed by modularly connecting `tile' CNN chips, each with a modest number of cells. The network operates in continuous time, has a PWL output function, and the cell connections (template values) are realized as sets of switchable unit and half-unit transconductors. Matching accuracy, including matching among chips from different manufacturing runs, and operation was verified on uncoupled and coupled templates.",

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year = "1998",

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note = "Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) ; Conference date: 31-05-1998 Through 03-06-1998",

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AB - A programmable cellular neural network has been designed in a 0.8 μ CMOS technology. An arbitrarily large analog CNN can be constructed by modularly connecting `tile' CNN chips, each with a modest number of cells. The network operates in continuous time, has a PWL output function, and the cell connections (template values) are realized as sets of switchable unit and half-unit transconductors. Matching accuracy, including matching among chips from different manufacturing runs, and operation was verified on uncoupled and coupled templates.

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

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T2 - Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6)

Y2 - 31 May 1998 through 3 June 1998

ER -

Modular g_m-C programmable CNN implementation

Abstract

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