Min-delay margin/error detection and correction for flip-flops and pulsed latches in 10-nm cmos

Pascal A. Meinerzhagen; Sandip Kundu; Andres Malavasi; Trang Nguyen; Muhammad M. Khellah; James W. Tschanz; Vivek De

doi:10.1109/lssc.2019.2935595

Min-delay margin/error detection and correction for flip-flops and pulsed latches in 10-nm cmos

Pascal A. Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad M. Khellah, James W. Tschanz, Vivek De

Intel

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

Min-delay (MID) error rates increase dramatically under aggressive voltage and technology scaling, limiting VMIN. Pulsed latches offer significant clocking power savings over flip-flops but further aggravate MID failures. This letter proposes MID margin/error detection and correction (M2/EDAC) for flip-flops and pulsed latches to reduce VMIN guard bands for voltage noise, temperature variation, and aging, and to detect and correct rare MID failures. Statistical data collection from a prototype in 10-nm tri-gate CMOS shows up to 122-mV VMIN reduction. Reliable pulsed latches enabled by M2/EDAC offer 12%-18% total dynamic power savings for logic blocks in 10-nm CMOS.

Original language	English
Article number	8877964
Pages (from-to)	147-150
Number of pages	4
Journal	IEEE Solid-State Circuits Letters
Volume	2
Issue number	9
DOIs	https://doi.org/10.1109/lssc.2019.2935595
State	Published - Sep 2019
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

10-nm tri-gate CMOS
Clock deskew
Error correction
MID margin detector (MD)/error detector (ED)
Min-delay (MID) failures
Reliable pulsed latches
VMIN reduction
Voltage adaptation

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10.1109/lssc.2019.2935595

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title = "Min-delay margin/error detection and correction for flip-flops and pulsed latches in 10-nm cmos",

abstract = "Min-delay (MID) error rates increase dramatically under aggressive voltage and technology scaling, limiting VMIN. Pulsed latches offer significant clocking power savings over flip-flops but further aggravate MID failures. This letter proposes MID margin/error detection and correction (M2/EDAC) for flip-flops and pulsed latches to reduce VMIN guard bands for voltage noise, temperature variation, and aging, and to detect and correct rare MID failures. Statistical data collection from a prototype in 10-nm tri-gate CMOS shows up to 122-mV VMIN reduction. Reliable pulsed latches enabled by M2/EDAC offer 12%-18% total dynamic power savings for logic blocks in 10-nm CMOS.",

keywords = "10-nm tri-gate CMOS, Clock deskew, Error correction, MID margin detector (MD)/error detector (ED), Min-delay (MID) failures, Reliable pulsed latches, VMIN reduction, Voltage adaptation",

author = "Meinerzhagen, {Pascal A.} and Sandip Kundu and Andres Malavasi and Trang Nguyen and Khellah, {Muhammad M.} and Tschanz, {James W.} and Vivek De",

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AU - Meinerzhagen, Pascal A.

AU - Kundu, Sandip

AU - Malavasi, Andres

AU - Nguyen, Trang

AU - Khellah, Muhammad M.

AU - Tschanz, James W.

AU - De, Vivek

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Min-delay margin/error detection and correction for flip-flops and pulsed latches in 10-nm cmos

Abstract

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Keywords

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