Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS

Pascal A. Meinerzhagen; Sandip Kundu; Andres Malavasi; Trang Nguyen; Muhammad M. Khellah; James W. Tschanz; Vivek De

doi:10.1109/lssc.2019.2935595

Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS

Pascal A. Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad M. Khellah, James W. Tschanz, Vivek De

Intel

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Min-delay (MID) error rates increase dramatically under aggressive voltage and technology scaling,limiting V_MIN. Pulsed latches offer significant clocking power savings over flip-flops but further aggravate MID failures. This letter proposes MID margin/error detection and correction (M2/EDAC) for flip-flops and pulsed latches to reduce V_MIN guard bands for voltage noise,temperature variation,and aging,and to detect and correct rare MID failures. Statistical data collection from a prototype in 10-nm tri-gate CMOS shows up to 122-mV V_MIN reduction. Reliable pulsed latches enabled by M2/EDAC offer 12%-18% total dynamic power savings for logic blocks in 10-nm CMOS.

Original language	English
Title of host publication	ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	147-150
Number of pages	4
ISBN (Electronic)	9781728115504
DOIs	https://doi.org/10.1109/lssc.2019.2935595
State	Published - Sep 2019
Externally published	Yes
Event	45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 - Cracow, Poland Duration: 23 Sep 2019 → 26 Sep 2019

Publication series

Name	ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

Conference

Conference	45th IEEE European Solid State Circuits Conference, ESSCIRC 2019
Country/Territory	Poland
City	Cracow
Period	23/09/19 → 26/09/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

Keywords

10-nm tri-gate CMOS
MID margin detector (MD)/error detector (ED)
V reduction
clock deskew
error correction
min-delay (MID) failures
reliable pulsed latches
voltage adaptation

Access to Document

10.1109/lssc.2019.2935595

Cite this

Meinerzhagen, P. A., Kundu, S., Malavasi, A., Nguyen, T., Khellah, M. M., Tschanz, J. W., & De, V. (2019). Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. In ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (pp. 147-150). Article 8902924 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/lssc.2019.2935595

Meinerzhagen, Pascal A. ; Kundu, Sandip ; Malavasi, Andres et al. / Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 147-150 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

@inproceedings{5a5cf8f2fe67465e9ca9791d94d94676,

title = "Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS",

abstract = "Min-delay (MID) error rates increase dramatically under aggressive voltage and technology scaling,limiting VMIN. Pulsed latches offer significant clocking power savings over flip-flops but further aggravate MID failures. This letter proposes MID margin/error detection and correction (M2/EDAC) for flip-flops and pulsed latches to reduce VMIN guard bands for voltage noise,temperature variation,and aging,and to detect and correct rare MID failures. Statistical data collection from a prototype in 10-nm tri-gate CMOS shows up to 122-mV VMIN reduction. Reliable pulsed latches enabled by M2/EDAC offer 12%-18% total dynamic power savings for logic blocks in 10-nm CMOS.",

keywords = "10-nm tri-gate CMOS, MID margin detector (MD)/error detector (ED), V reduction, clock deskew, error correction, min-delay (MID) failures, reliable pulsed latches, voltage adaptation",

author = "Meinerzhagen, {Pascal A.} and Sandip Kundu and Andres Malavasi and Trang Nguyen and Khellah, {Muhammad M.} and Tschanz, {James W.} and Vivek De",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 ; Conference date: 23-09-2019 Through 26-09-2019",

year = "2019",

month = sep,

doi = "10.1109/lssc.2019.2935595",

language = "אנגלית",

series = "ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "147--150",

booktitle = "ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference",

address = "ארצות הברית",

}

Meinerzhagen, PA, Kundu, S, Malavasi, A, Nguyen, T, Khellah, MM, Tschanz, JW & De, V 2019, Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference., 8902924, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 147-150, 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, 23/09/19. https://doi.org/10.1109/lssc.2019.2935595

Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. / Meinerzhagen, Pascal A.; Kundu, Sandip; Malavasi, Andres et al.
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2019. p. 147-150 8902924 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS

AU - Meinerzhagen, Pascal A.

AU - Kundu, Sandip

AU - Malavasi, Andres

AU - Nguyen, Trang

AU - Khellah, Muhammad M.

AU - Tschanz, James W.

AU - De, Vivek

PY - 2019/9

Y1 - 2019/9

N2 - Min-delay (MID) error rates increase dramatically under aggressive voltage and technology scaling,limiting VMIN. Pulsed latches offer significant clocking power savings over flip-flops but further aggravate MID failures. This letter proposes MID margin/error detection and correction (M2/EDAC) for flip-flops and pulsed latches to reduce VMIN guard bands for voltage noise,temperature variation,and aging,and to detect and correct rare MID failures. Statistical data collection from a prototype in 10-nm tri-gate CMOS shows up to 122-mV VMIN reduction. Reliable pulsed latches enabled by M2/EDAC offer 12%-18% total dynamic power savings for logic blocks in 10-nm CMOS.

AB - Min-delay (MID) error rates increase dramatically under aggressive voltage and technology scaling,limiting VMIN. Pulsed latches offer significant clocking power savings over flip-flops but further aggravate MID failures. This letter proposes MID margin/error detection and correction (M2/EDAC) for flip-flops and pulsed latches to reduce VMIN guard bands for voltage noise,temperature variation,and aging,and to detect and correct rare MID failures. Statistical data collection from a prototype in 10-nm tri-gate CMOS shows up to 122-mV VMIN reduction. Reliable pulsed latches enabled by M2/EDAC offer 12%-18% total dynamic power savings for logic blocks in 10-nm CMOS.

KW - 10-nm tri-gate CMOS

KW - MID margin detector (MD)/error detector (ED)

KW - V reduction

KW - clock deskew

KW - error correction

KW - min-delay (MID) failures

KW - reliable pulsed latches

KW - voltage adaptation

UR - http://www.scopus.com/inward/record.url?scp=85075910013&partnerID=8YFLogxK

U2 - 10.1109/lssc.2019.2935595

DO - 10.1109/lssc.2019.2935595

M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???

AN - SCOPUS:85075910013

T3 - ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

SP - 147

EP - 150

BT - ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019

Y2 - 23 September 2019 through 26 September 2019

ER -

Meinerzhagen PA, Kundu S, Malavasi A, Nguyen T, Khellah MM, Tschanz JW et al. Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. In ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc. 2019. p. 147-150. 8902924. (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference). doi: 10.1109/lssc.2019.2935595

Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

Other files and links

Fingerprint

Cite this