Abstract
Edge-AI applications face huge challenges in resource-constrained environments, particularly in enhancing computational efficiency within bandwidth limitations. This work proposes the Logarithmic-Posit-enabled Reconfigurable edgeAI Engine (LPRE) that enhances hardware efficiency without compromising accuracy. The proposed architecture utilizes time-multiplexed dynamically configurable single-layer hardware to balance resource reuse and bandwidth for multi-layer perceptron and CNN models. Evaluations on LeNet-5 using MNIST demonstrate that LPRE achieves up to 4× throughput enhancement at 8-bit precision with negligible accuracy loss (compared to FP32 baseline), while requiring up to 80% and 50% fewer resources than fixed-point arithmetic and state-of-the-art works, respectively. The design is viable for various edge-AI applications, such as real-time number plate recognition, offering scalable, energy-efficient IoT solutions.
| Original language | English |
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| Title of host publication | ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9798350356830 |
| DOIs | |
| State | Published - 2025 |
| Event | 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 - London, United Kingdom Duration: 25 May 2025 → 28 May 2025 |
Publication series
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| ISSN (Print) | 0271-4310 |
Conference
| Conference | 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 |
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| Country/Territory | United Kingdom |
| City | London |
| Period | 25/05/25 → 28/05/25 |
Bibliographical note
Publisher Copyright:© 2025 IEEE.
Keywords
- Edge-AI accelerators
- Multi-layer perceptrons
- Posit MAC
- Quantization
- Reconfigurable computing