LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine

  • Omkar Kokane
  • , Mukul Lokhande
  • , Gopal Raut
  • , Adam Teman
  • , Santosh Kumar Vishvakarma

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Edge-AI applications face huge challenges in resource-constrained environments, particularly in enhancing computational efficiency within bandwidth limitations. This work proposes the Logarithmic-Posit-enabled Reconfigurable edgeAI Engine (LPRE) that enhances hardware efficiency without compromising accuracy. The proposed architecture utilizes time-multiplexed dynamically configurable single-layer hardware to balance resource reuse and bandwidth for multi-layer perceptron and CNN models. Evaluations on LeNet-5 using MNIST demonstrate that LPRE achieves up to 4× throughput enhancement at 8-bit precision with negligible accuracy loss (compared to FP32 baseline), while requiring up to 80% and 50% fewer resources than fixed-point arithmetic and state-of-the-art works, respectively. The design is viable for various edge-AI applications, such as real-time number plate recognition, offering scalable, energy-efficient IoT solutions.

Original languageEnglish
Title of host publicationISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350356830
DOIs
StatePublished - 2025
Event2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 - London, United Kingdom
Duration: 25 May 202528 May 2025

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
Country/TerritoryUnited Kingdom
CityLondon
Period25/05/2528/05/25

Bibliographical note

Publisher Copyright:
© 2025 IEEE.

Keywords

  • Edge-AI accelerators
  • Multi-layer perceptrons
  • Posit MAC
  • Quantization
  • Reconfigurable computing

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