Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI

Ramiro Taco; Itamar Levi; Marco Lanuzza; Alexander Fish

doi:10.1109/s3s.2015.7333515

Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI

Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish

University of Calabria

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this paper, a low voltage ripple-carry adder (RCA), designed for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology, is proposed. The circuit synergistically benefits from low-granularity back-bias control to improve performance in conjunction with the integration of both NMOS and PMOS devices into a common well configuration which allows highly efficient area utilization. The design was compared over standard CMOS and DTMOS solutions. Comparative post-layout results demonstrate that the suggested approach improves energy consumption up to 57% in comparison to the equivalent DTMOS design and reduces delay up to 30% with similar energy consumption, when compared to the conventional CMOS implementation. In addition, reduced silicon area occupancy is achieved.

Original language	English
Title of host publication	2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509002597
DOIs	https://doi.org/10.1109/s3s.2015.7333515
State	Published - 20 Nov 2015
Event	IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 - Rohnert Park, United States Duration: 5 Oct 2015 → 8 Oct 2015

Publication series

Name	2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

Conference

Conference	IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
Country/Territory	United States
City	Rohnert Park
Period	5/10/15 → 8/10/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

FD-SOI
gate-level body biasing
single well

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/s3s.2015.7333515

Cite this

Taco, R., Levi, I., Lanuzza, M., & Fish, A. (2015). Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 Article 7333515 (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/s3s.2015.7333515

Taco, Ramiro ; Levi, Itamar ; Lanuzza, Marco et al. / Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI. 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc., 2015. (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015).

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title = "Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI",

abstract = "In this paper, a low voltage ripple-carry adder (RCA), designed for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology, is proposed. The circuit synergistically benefits from low-granularity back-bias control to improve performance in conjunction with the integration of both NMOS and PMOS devices into a common well configuration which allows highly efficient area utilization. The design was compared over standard CMOS and DTMOS solutions. Comparative post-layout results demonstrate that the suggested approach improves energy consumption up to 57% in comparison to the equivalent DTMOS design and reduces delay up to 30% with similar energy consumption, when compared to the conventional CMOS implementation. In addition, reduced silicon area occupancy is achieved.",

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author = "Ramiro Taco and Itamar Levi and Marco Lanuzza and Alexander Fish",

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Taco, R, Levi, I, Lanuzza, M & Fish, A 2015, Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI. in 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015., 7333515, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015, Institute of Electrical and Electronics Engineers Inc., IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015, Rohnert Park, United States, 5/10/15. https://doi.org/10.1109/s3s.2015.7333515

Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI. / Taco, Ramiro; Levi, Itamar; Lanuzza, Marco et al.
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7333515 (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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PY - 2015/11/20

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N2 - In this paper, a low voltage ripple-carry adder (RCA), designed for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology, is proposed. The circuit synergistically benefits from low-granularity back-bias control to improve performance in conjunction with the integration of both NMOS and PMOS devices into a common well configuration which allows highly efficient area utilization. The design was compared over standard CMOS and DTMOS solutions. Comparative post-layout results demonstrate that the suggested approach improves energy consumption up to 57% in comparison to the equivalent DTMOS design and reduces delay up to 30% with similar energy consumption, when compared to the conventional CMOS implementation. In addition, reduced silicon area occupancy is achieved.

AB - In this paper, a low voltage ripple-carry adder (RCA), designed for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology, is proposed. The circuit synergistically benefits from low-granularity back-bias control to improve performance in conjunction with the integration of both NMOS and PMOS devices into a common well configuration which allows highly efficient area utilization. The design was compared over standard CMOS and DTMOS solutions. Comparative post-layout results demonstrate that the suggested approach improves energy consumption up to 57% in comparison to the equivalent DTMOS design and reduces delay up to 30% with similar energy consumption, when compared to the conventional CMOS implementation. In addition, reduced silicon area occupancy is achieved.

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Taco R, Levi I, Lanuzza M, Fish A. Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7333515. (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015). doi: 10.1109/s3s.2015.7333515

Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI

Abstract

Publication series

Conference

Bibliographical note

Keywords

UN SDGs

Access to Document

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