TY - JOUR
T1 - Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI
AU - Taco, Ramiro
AU - Levi, Itamar
AU - Lanuzza, Marco
AU - Fish, Alexander
N1 - Publisher Copyright:
© 2015 Elsevier Ltd. All rights reserved.
PY - 2016/3/1
Y1 - 2016/3/1
N2 - In this paper, the recently proposed gate level body bias (GLBB) technique is evaluated for low voltage logic design in state-of-the-art 28 nm ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The inherent benefits of the low-granularity body-bias control, provided by the GLBB approach, are emphasized by the efficiency of forward body bias (FBB) in the FD-SOI technology. In addition, the possibility to integrate PMOS and NMOS devices into a single common well configuration allows significant area reduction, as compared to an equivalent triple well implementation. Some arithmetic circuits were designed using GLBB approach and compared to their conventional CMOS and DTMOS counterparts under different running conditions at low voltage regime. Simulation results shows that, for 300 mV of supply voltage, a 4 × 4-bit GLBB Baugh Wooley multiplier allows performance improvement of about 30% and area reduction of about 35%, while maintaining low energy consumption as compared to the conventional CMOs\DTMOS solutions. Performance and energy benefits are maintained over a wide range of process-voltage-temperature (PVT) variations.
AB - In this paper, the recently proposed gate level body bias (GLBB) technique is evaluated for low voltage logic design in state-of-the-art 28 nm ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The inherent benefits of the low-granularity body-bias control, provided by the GLBB approach, are emphasized by the efficiency of forward body bias (FBB) in the FD-SOI technology. In addition, the possibility to integrate PMOS and NMOS devices into a single common well configuration allows significant area reduction, as compared to an equivalent triple well implementation. Some arithmetic circuits were designed using GLBB approach and compared to their conventional CMOS and DTMOS counterparts under different running conditions at low voltage regime. Simulation results shows that, for 300 mV of supply voltage, a 4 × 4-bit GLBB Baugh Wooley multiplier allows performance improvement of about 30% and area reduction of about 35%, while maintaining low energy consumption as compared to the conventional CMOs\DTMOS solutions. Performance and energy benefits are maintained over a wide range of process-voltage-temperature (PVT) variations.
KW - Dynamic body biasing
KW - Low-voltage logic design
KW - UTBB FD-SOI
UR - http://www.scopus.com/inward/record.url?scp=84954026961&partnerID=8YFLogxK
U2 - 10.1016/j.sse.2015.11.013
DO - 10.1016/j.sse.2015.11.013
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AN - SCOPUS:84954026961
SN - 0038-1101
VL - 117
SP - 185
EP - 192
JO - Solid-State Electronics
JF - Solid-State Electronics
ER -