Low-Voltage DML

Itamar Levi; Alexander Fish

doi:10.1007/978-3-030-40786-5_4

Low-Voltage DML

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

This chapter examines DML performance, energy consumption, static noise margins, delay distribution, robustness, and other design metrics under low-voltage operation. It still focuses on the gate level and DML operations in subthreshold and near-threshold regions...

Original language	English
Title of host publication	Dual Mode Logic
Place of Publication	Cham, Switzerland
Publisher	Springer
Pages	59-73
Number of pages	15
DOIs	https://doi.org/10.1007/978-3-030-40786-5_4
State	Published - 16 Dec 2020

Keywords

Subthreshold (ST)
Near-threshold (NT)
Transregional model
CMOS
Dynamic logic
Logical effort
Strong inversion
On-current
Sizing
Stacked transistors
Adder
Monte Carlo
Robustness
Static noise margin (SNM)
Delay–energy
DML

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1007/978-3-030-40786-5_4

Cite this

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KW - Strong inversion

KW - On-current

KW - Sizing

KW - Stacked transistors

KW - Adder

KW - Monte Carlo

KW - Robustness

KW - Static noise margin (SNM)

KW - Delay–energy

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Low-Voltage DML

Abstract

Keywords

UN SDGs

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