Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel

Arthur Spivak, Adam Teman, Alexander Belenky, Orly Yadid-Pecht, Alexander Fish

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

Original languageEnglish
Pages (from-to)10067-10085
Number of pages19
JournalSensors
Volume12
Issue number8
DOIs
StatePublished - Aug 2012
Externally publishedYes

Keywords

  • CMOS
  • Image sensor
  • Low power
  • SNR
  • Snapshot
  • Strong inversion
  • Sub-threshold
  • Wide dynamic range

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