TY - JOUR
T1 - Low-power global/rolling shutter image sensors in silicon on sapphire technology
AU - Fish, Alexander
AU - Avner, Evgeny
AU - Yadid-Pecht, Orly
PY - 2005
Y1 - 2005
N2 - A variety of low-power global shutter (snapshot) and rolling shutter Active Pixel Sensors (APS) in Silicon on Sapphire (SOS) technology are presented. Utilizing the floating gate NMOS photodetector, operating in a lateral bipolar transistor (LBT) mode, the described imagers are expected to achieve high responsivity and are mostly suitable for low-power applications. The proposed global shutter sensors enable imaging of fast moving objects in the field of view. Power dissipation of the proposed imagers is reduced by employing an advanced Gate-Diffusion Input (GDI) technique, used for the sensors digital periphery implementation. A test chip, consisting of four different 32*32 global shutter and rolling shutter image sensor arrays, operating at power supply, ranging from 1.2V to 3V, has been implemented in a Peregrine's 0.5μm SOS technology. System architectures and operation of the presented imagers are discussed, and a comparison with existing APS structures is presented as well.
AB - A variety of low-power global shutter (snapshot) and rolling shutter Active Pixel Sensors (APS) in Silicon on Sapphire (SOS) technology are presented. Utilizing the floating gate NMOS photodetector, operating in a lateral bipolar transistor (LBT) mode, the described imagers are expected to achieve high responsivity and are mostly suitable for low-power applications. The proposed global shutter sensors enable imaging of fast moving objects in the field of view. Power dissipation of the proposed imagers is reduced by employing an advanced Gate-Diffusion Input (GDI) technique, used for the sensors digital periphery implementation. A test chip, consisting of four different 32*32 global shutter and rolling shutter image sensor arrays, operating at power supply, ranging from 1.2V to 3V, has been implemented in a Peregrine's 0.5μm SOS technology. System architectures and operation of the presented imagers are discussed, and a comparison with existing APS structures is presented as well.
UR - http://www.scopus.com/inward/record.url?scp=51749108883&partnerID=8YFLogxK
U2 - 10.1109/iscas.2005.1464654
DO - 10.1109/iscas.2005.1464654
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AN - SCOPUS:51749108883
SN - 0271-4310
SP - 580
EP - 583
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 1464654
T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
Y2 - 23 May 2005 through 26 May 2005
ER -