Low-power FPGAs based on resistive memories

Xifan Tang, Somayyeh Rahimian Omam, Pascal Meinerzhagen, Pierre Emmanuel Gaillardon, Giovanni De Micheli

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review


Compared to Application-Specific Integrated Circuits (ASICs), Static Random Access Memory (SRAM)-based Field Programmable Gate Arrays (FPGAs) can be customized to any user application but at the cost of approximately 20× bigger area, 4× longer delay, and 12× higher power consumption [1]. In modern FPGA architectures, the versatile programmable routing architecture accounts for about 70% of the area, 80% of the delay and 60% of the power of the entire chip [2]. Nowadays, power consumption stands as a serious barrier for the distribution of FPGAs in a large set of consumer applications requiring Ultra-Low Power (ULP) System-on-Chip (SoCs). Previous works [3, 4, 5] demonstrate that employing near/sub-Vt supply voltage for SRAMbased FPGA designs saves up to 50% of the power consumption. However, low-power SRAM-based FPGAs generally suffer from large delay degradation (up to 2×) due to the low supply voltage.

Original languageEnglish
Title of host publicationReconfigurable Logic
Subtitle of host publicationArchitecture, Tools, and Applications
PublisherCRC Press
Number of pages34
ISBN (Electronic)9781482262193
ISBN (Print)9781482262186
StatePublished - 1 Jan 2015
Externally publishedYes

Bibliographical note

Publisher Copyright:
© 2016 by Taylor & Francis Group, LLC.


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