TY - GEN
T1 - Low noise linear voltage regulator for use as an on-chip PLL supply in microprocessors
AU - Shor, Joseph
PY - 2010
Y1 - 2010
N2 - A novel on-chip linear voltage regulator (VR), for use as PLL power supply is described. This voltage regulator exhibits a Power Supply Rejection Ratio (PSRR) of > 40dB and low thermal noise. Accurate current control enables optimized power and performance. These properties enable the VR to be utilized in PLL's without adding any deterministic and random jitter. The VR has been designed and characterized in Intel's recent leading-edge purely digital process.
AB - A novel on-chip linear voltage regulator (VR), for use as PLL power supply is described. This voltage regulator exhibits a Power Supply Rejection Ratio (PSRR) of > 40dB and low thermal noise. Accurate current control enables optimized power and performance. These properties enable the VR to be utilized in PLL's without adding any deterministic and random jitter. The VR has been designed and characterized in Intel's recent leading-edge purely digital process.
UR - http://www.scopus.com/inward/record.url?scp=77956005745&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2010.5537431
DO - 10.1109/ISCAS.2010.5537431
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AN - SCOPUS:77956005745
SN - 9781424453085
T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
SP - 841
EP - 844
BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Y2 - 30 May 2010 through 2 June 2010
ER -