Low dropout voltage regulator integrated with digital power gate driver

J. Shor; K. Luria; A. Lyakhov; M. Zelikson

Low dropout voltage regulator integrated with digital power gate driver

J. Shor (Inventor)
, K. Luria (Inventor)
, A. Lyakhov (Inventor)
, M. Zelikson (Inventor)

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Intel Corp.

Research output: Patent

Abstract

Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.

Original language	American English
State	Published - 2018

Cite this

@misc{6d23ab37921a4686bbfa807e7fc057fe,

title = "Low dropout voltage regulator integrated with digital power gate driver",

abstract = "Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.",

author = "J. Shor and K. Luria and A. Lyakhov and M. Zelikson",

year = "2018",

language = "American English",

publisher = "Washington, DC: U.S. Patent and Trademark Office",

type = "Patent",

}

TY - PAT

T1 - Low dropout voltage regulator integrated with digital power gate driver

AU - Shor, J.

AU - Luria, K.

AU - Lyakhov, A.

AU - Zelikson, M.

PY - 2018

Y1 - 2018

N2 - Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.

AB - Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.

UR - https://patents.google.com/patent/US20160202714A1/en

M3 - Patent

PB - Washington, DC: U.S. Patent and Trademark Office

ER -

Low dropout voltage regulator integrated with digital power gate driver

Abstract

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