Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory with a 1% Area and Less Than 5% Latency and Power Overheads

Yoav Weizman, Robert Giterman, Oron Chertkow, Maoz Wicentowski, Itamar Levi, Ilan Sever, Ishai Kehati, Osnat Keren, Alexander Fish

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


Side-channel attacks constitute a concrete threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with 6T SRAM macrocells often dominate the area and power consumption of these SoCs. Regardless of the computational platform, the side-channel sensitivity of low-hierarchy cache memories can incur significant overhead to protect the memory content (i.e., data encryption, data masking, etc.). In this manuscript, we provide a silicon proof of the effectiveness of a low cost side-channel attack protection that is embedded within the memory macro to achieve a significant reduction in information leakage. The proposed solution incorporates low-cost impedance randomization units, which are integrated into the periphery of a conventional 6T SRAM macro in fine-grain memory partitions, providing possible protection against electromagnetic adversaries. Various blocks of unprotected and protected SRAM macros were designed and fabricated in a 55 nm test-chip. The protected ones had little as 1% area overhead and less than 5% performance and power penalties compared to a conventional SRAM design. To evaluate the security of the proposed solution, we applied a robust mutual information metric and an adaptation to the memory context to enhance this evaluation framework. Assessment of the protected memory demonstrated a significant information leakage reduction from 8 bits of information exposed after only 100 cycles of attack to less than 1.5 bits of mutual information after 160K traces. The parametric nature of the protection mechanisms are discussed while specifying the proposed design parameters. Overall, the proposed methodology enables designs with higher security-level at a minimal cost.

Original languageEnglish
Article number9453841
Pages (from-to)91764-91776
Number of pages13
JournalIEEE Access
StatePublished - 2021

Bibliographical note

Funding Information:
This work was supported in part by the Israel Science Foundation under Grant 2511/20 and Grant 1266/20, and in part by the Israel Innovation Authority in the frame of the Magneton Program.

Publisher Copyright:
© 2013 IEEE.


  • Secured Static Random Access Memories (SRAM)
  • hardware security
  • power analysis
  • secured memory


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