Low-cost pseudoasynchronous circuit design style with reduced exploitable side information

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12 Scopus citations

Abstract

Leakage of information through the power supply current has become a major factor in logic design. In this paper, a low cost and simple to employ design methodology dubbed pseudoasynchronous is presented. This design style combines the security advantages of asynchronous circuits with the ease of synchronous circuit design. Randomization and datadependencies (DD) are utilized to hide information leakage from the current dissipation, and hence making the critical synchronization of power supply current traces hard to do. In addition, randomization and DD are utilized for both time-domain hiding of information leakage during the active region (dynamic currents) and for amplitude-domain hiding of information leakage during the static-region (leakage currents). The main advantages of this new approach are low area cost, reduced signal, and increased noise. Circuit-level analyses show that it is harder to exploit the information leakage from internal signals of the proposed design than from CMOS-based synchronous designs or other forms of time-domain hiding countermeasures.

Original languageEnglish
Pages (from-to)82-95
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume26
Issue number1
DOIs
StatePublished - Jan 2018

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Keywords

  • Asynchronous
  • Data-dependence
  • Globally asynchronous locally synchronous (GALS)
  • Hiding
  • Information leakage
  • Power nalysis (PA)
  • Pseudoasynchronous (pAsynch)
  • Side-channel-analysis countermeasures
  • Synchronous

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