Logical effort for CMOS-based dual mode logic gates

Keyphrases

• Logic Gates 100%
• Dual Mode Logic 100%
• Logical Effort 100%
• Dynamic Mode 50%
• Logic Family 50%
• Delay Estimation 33%
• Proposed Methodology 33%
• High Performance 16%
• Operation Mode 16%
• Path Length 16%
• Two-mode 16%
• Mathematical Analysis 16%
• Low Power Dissipation 16%
• 40nm CMOS 16%
• Optimum number 16%
• Delay Optimization 16%
• Design Optimization 16%
• Static Mode 16%
• Very Low Power 16%
• Gate Sizing 16%
• Stage number 16%
• Length Minimization 16%
• Effort Model 16%
• Stage-gate 16%
• Static Logic 16%
• Parameter Optimization 16%
• Sizing Factor 16%
• Factor Estimation 16%
• Clocked Transistor 16%

Computer Science

• Logic Gate 100%
• Logic Family 100%
• Logical Effort 100%
• And Gate 33%
• Power Dissipation 33%
• Delay Minimization 33%
• Design Optimization 33%

Engineering

• Logic Gate 100%
• Mode Dynamic 100%
• Delay Estimation 66%
• Pathlength 33%
• Energy Dissipation 33%
• Optimum Number 33%
• Design Optimization 33%