Logical effort for CMOS-based dual mode logic gates

Itamar Levi, Alexander Belenky, Alexander Fish

Research output: Contribution to journalArticlepeer-review

30 Scopus citations


Recently, a novel dual mode logic (DML) family was proposed. This logic allows operation in two modes: 1) static and 2) dynamic modes. DML gates, which can be switched between these modes on-the-fly, feature very low power dissipation in the static mode and high performance in the dynamic mode. A basic DML gate is very simple and is composed of any static logic family gate and an additional clocked transistor. In this paper, we introduce the logical effort (LE) methodology for the CMOS-based DML family. The proposed methodology allows path length minimization, delay optimization, and delay estimation of DML logic. This is done by development of complete and approximated LE models, which allows easy extraction of design optimization parameters, such as optimum number of stages, gates sizing factors, and delay estimations. The proposed optimization is shown for the dynamic mode of operation. Theoretical mathematical analysis is presented, and efficiency of the proposed methodology is shown in a standard 40-nm CMOS process.

Original languageEnglish
Article number6515657
Pages (from-to)1042-1053
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number5
StatePublished - May 2014


  • Dual mode logic
  • high performance
  • logical effort
  • low power
  • optimization.


Dive into the research topics of 'Logical effort for CMOS-based dual mode logic gates'. Together they form a unique fingerprint.

Cite this