Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET

Netanel Shavit; Inbal Stanger; Ramiro Taco; Marco Lanuzza; Alexander Fish

doi:10.1109/iscas51556.2021.9401241

Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET

Netanel Shavit, Inbal Stanger, Ramiro Taco, Marco Lanuzza, Alexander Fish

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The Dual Mode Logic (DML) defines run-time adaptive digital architectures that switch to either improved performance or lower energy consumption as a function of actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16x16-bit Booth multiplier fabricated as a part of an ultra-low power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same design saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

Original language	English
Title of host publication	2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728192017
DOIs	https://doi.org/10.1109/iscas51556.2021.9401241
State	Published - 2021
Event	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of Duration: 22 May 2021 → 28 May 2021

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2021-May
ISSN (Print)	0271-4310

Conference

Conference	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Country/Territory	Korea, Republic of
City	Daegu
Period	22/05/21 → 28/05/21

Bibliographical note

Publisher Copyright:
© 2021 IEEE

Funding

This work was funded by the Israel Innovation Authority in the frame of the Hiper consortium.

Funders	Funder number
Israel Innovation Authority in the frame of the Hiper consortium

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/iscas51556.2021.9401241

Cite this

Shavit, N., Stanger, I., Taco, R., Lanuzza, M., & Fish, A. (2021). Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings Article 9401241 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/iscas51556.2021.9401241

Shavit, Netanel ; Stanger, Inbal ; Taco, Ramiro et al. / Live demonstration : A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET. 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. (Proceedings - IEEE International Symposium on Circuits and Systems).

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abstract = "The Dual Mode Logic (DML) defines run-time adaptive digital architectures that switch to either improved performance or lower energy consumption as a function of actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16x16-bit Booth multiplier fabricated as a part of an ultra-low power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same design saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.",

author = "Netanel Shavit and Inbal Stanger and Ramiro Taco and Marco Lanuzza and Alexander Fish",

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Shavit, N, Stanger, I, Taco, R, Lanuzza, M & Fish, A 2021, Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET. in 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings., 9401241, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2021-May, Institute of Electrical and Electronics Engineers Inc., 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, Korea, Republic of, 22/05/21. https://doi.org/10.1109/iscas51556.2021.9401241

Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET. / Shavit, Netanel; Stanger, Inbal; Taco, Ramiro et al.
2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9401241 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Shavit N, Stanger I, Taco R, Lanuzza M, Fish A. Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. 9401241. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/iscas51556.2021.9401241

Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET

Abstract

Publication series

Conference

Bibliographical note

Funding

UN SDGs

Access to Document

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