The unique ability of dual mode logic (DML) to self-adapt to computational needs by providing high speed and/or low energy consumption is demonstrated for the first time by silicon measurements in 28nm FD-SOI. At the gate level, the DML design offers the possibility to operate either in the static mode to save energy, or in the dynamic mode to increase speed albeit with higher delay or energy consumption, respectively. In this demonstration, the two operational modes are dynamically managed by a self-adjustment mechanism to increase speed or reduce energy of the design at run-time. As a test case a two-stage pipelined multiply-accumulate (MAC) circuit was selected to assess the advantages of DML in terms of speed, energy and area as compared to a conventional CMOS design. We show that the self-adjusted DML MAC achieves both a performance boost of up to 92% and 16% less energy consumption than the equivalent standard CMOS implementation. The energy saved can be even greater (-35%) when the low-power (fully static) mode is enabled. In addition, the DML MAC occupies 25% less area.
|Title of host publication
|2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
|Institute of Electrical and Electronics Engineers Inc.
|Published - 2019
|2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan
Duration: 26 May 2019 → 29 May 2019
|Proceedings - IEEE International Symposium on Circuits and Systems
|2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
|26/05/19 → 29/05/19
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