Live Demo: An 88fJ / 40 MHz [0.4V] – 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI

A. Fish, R. Taco, I. Levi, M. Lanuzza

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Original languageAmerican English
Title of host publication2019 IEEE International Symposium on Circuits and Systems (ISCAS)
StatePublished - 2019

Bibliographical note

Place of conference:Sapporo, Japan

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