IO buffer for high performance, low-power applications

Joseph S. Shor; Yachin Afek; Eytan Engel

IO buffer for high performance, low-power applications

Joseph S. Shor
, Yachin Afek
, Eytan Engel

Motorola

Research output: Contribution to journal › Conference article › peer-review

12 Scopus citations

Abstract

An IO Buffer architecture is shown which provides fast output transitions as well as efficient voltage level shifting from the chip interior. The buffer contains a feedback circuit which damps ringing associated with supply bounce. Fast voltage converters are demonstrated which allow the core to operate at a lower voltage (1.5 V), without significant delay penalties on the IO (at 3.6 V). These novel circuits are important for high performance, low power applications, such as wireless DSPs.

Original language	English
Pages (from-to)	595-598
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
State	Published - 1997
Externally published	Yes
Event	Proceedings of the 1997 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA Duration: 5 May 1997 → 8 May 1997

Cite this

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title = "IO buffer for high performance, low-power applications",

abstract = "An IO Buffer architecture is shown which provides fast output transitions as well as efficient voltage level shifting from the chip interior. The buffer contains a feedback circuit which damps ringing associated with supply bounce. Fast voltage converters are demonstrated which allow the core to operate at a lower voltage (1.5 V), without significant delay penalties on the IO (at 3.6 V). These novel circuits are important for high performance, low power applications, such as wireless DSPs.",

author = "Shor, \{Joseph S.\} and Yachin Afek and Eytan Engel",

year = "1997",

language = "אנגלית",

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journal = "Proceedings of the Custom Integrated Circuits Conference",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1997 IEEE Custom Integrated Circuits Conference ; Conference date: 05-05-1997 Through 08-05-1997",

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AU - Shor, Joseph S.

AU - Afek, Yachin

AU - Engel, Eytan

PY - 1997

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N2 - An IO Buffer architecture is shown which provides fast output transitions as well as efficient voltage level shifting from the chip interior. The buffer contains a feedback circuit which damps ringing associated with supply bounce. Fast voltage converters are demonstrated which allow the core to operate at a lower voltage (1.5 V), without significant delay penalties on the IO (at 3.6 V). These novel circuits are important for high performance, low power applications, such as wireless DSPs.

AB - An IO Buffer architecture is shown which provides fast output transitions as well as efficient voltage level shifting from the chip interior. The buffer contains a feedback circuit which damps ringing associated with supply bounce. Fast voltage converters are demonstrated which allow the core to operate at a lower voltage (1.5 V), without significant delay penalties on the IO (at 3.6 V). These novel circuits are important for high performance, low power applications, such as wireless DSPs.

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AN - SCOPUS:0030673941

SN - 0886-5930

SP - 595

EP - 598

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

T2 - Proceedings of the 1997 IEEE Custom Integrated Circuits Conference

Y2 - 5 May 1997 through 8 May 1997

ER -

IO buffer for high performance, low-power applications

Abstract

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