IO Buffer for High Performance, Low Power Applications

J. Shor; Yachin Afek; Eytan Engel

IO Buffer for High Performance, Low Power Applications

J. Shor
, Yachin Afek
, Eytan Engel

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

An IO buffer architecture is shown which provides fast output transitions as well as efficient voltage level shifting from the chip interior. The buffer contains a feedback circuit which damps ringing associated with supply bounce. Fast voltage converters are demonstrated which allow the core to operate at a lower voltage (1.8 V), without significant delay penalties on the IO (at 3.6 V). These novel circuits are important for high performance, low power applications, such as wireless DSPs

Original language	American English
Title of host publication	Custom Integrated Circuits Conference
Publisher	IEEE
State	Published - 1997

Bibliographical note

Place of conference:USA

Cite this

@inproceedings{f37abb7aec304598b662cf6f3adf5126,

title = "IO Buffer for High Performance, Low Power Applications",

abstract = "An IO buffer architecture is shown which provides fast output transitions as well as efficient voltage level shifting from the chip interior. The buffer contains a feedback circuit which damps ringing associated with supply bounce. Fast voltage converters are demonstrated which allow the core to operate at a lower voltage (1.8 V), without significant delay penalties on the IO (at 3.6 V). These novel circuits are important for high performance, low power applications, such as wireless DSPs",

author = "J. Shor and Yachin Afek and Eytan Engel",

note = "Place of conference:USA",

year = "1997",

language = "American English",

booktitle = "Custom Integrated Circuits Conference",

publisher = "IEEE",

}

TY - GEN

T1 - IO Buffer for High Performance, Low Power Applications

AU - Shor, J.

AU - Afek, Yachin

AU - Engel, Eytan

N1 - Place of conference:USA

PY - 1997

Y1 - 1997

N2 - An IO buffer architecture is shown which provides fast output transitions as well as efficient voltage level shifting from the chip interior. The buffer contains a feedback circuit which damps ringing associated with supply bounce. Fast voltage converters are demonstrated which allow the core to operate at a lower voltage (1.8 V), without significant delay penalties on the IO (at 3.6 V). These novel circuits are important for high performance, low power applications, such as wireless DSPs

AB - An IO buffer architecture is shown which provides fast output transitions as well as efficient voltage level shifting from the chip interior. The buffer contains a feedback circuit which damps ringing associated with supply bounce. Fast voltage converters are demonstrated which allow the core to operate at a lower voltage (1.8 V), without significant delay penalties on the IO (at 3.6 V). These novel circuits are important for high performance, low power applications, such as wireless DSPs

UR - https://scholar.google.co.il/scholar?q=IO+Buffer+for+High+Performance%2C+Low+Power+Applications&btnG=&hl=en&as_sdt=0%2C5

M3 - Conference contribution

BT - Custom Integrated Circuits Conference

PB - IEEE

ER -

IO Buffer for High Performance, Low Power Applications

Abstract

Bibliographical note

Other files and links

Fingerprint

Cite this