IO Buffer for High Performance, Low Power Applications

J. Shor, Yachin Afek, Eytan Engel

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


An IO buffer architecture is shown which provides fast output transitions as well as efficient voltage level shifting from the chip interior. The buffer contains a feedback circuit which damps ringing associated with supply bounce. Fast voltage converters are demonstrated which allow the core to operate at a lower voltage (1.8 V), without significant delay penalties on the IO (at 3.6 V). These novel circuits are important for high performance, low power applications, such as wireless DSPs
Original languageAmerican English
Title of host publicationCustom Integrated Circuits Conference
StatePublished - 1997

Bibliographical note

Place of conference:USA


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