Investigation on Threshold Voltage Instability of ZnO TFT in the presence of Gaussian Distributed Grain Boundary Traps

Traps in the ZnO thin film transistors (TFTs) affect the electrical characteristics of the device. They are primarily due to the disordered nature of the deposited polycrystalline semiconductor channel, i.e., ZnO, or present at ZnO and gate-dielectric interface. This work studies the effect of grain boundary (GB) traps in single-gate ZnO TFT using Sentaurus TCAD. The distribution of grain boundary and interface traps is assumed to be Gaussian within the energy band gap of ZnO. The impact of varying peak concentration (N_a), the number of GBs, and the effect of their positional variation (E_mid) within the band gap of ZnO has been examined. As the acceptor-like trap density increases, the threshold voltage (VTH) also increases while the subthreshold swing degrades. Also, the location of the peak trap concentration with respect to the conduction band edge (E_c) affects V_TH. The deeper the location of the peak within the energy band gap of ZnO, the more the change in threshold voltage (V_TH). For instance, for GB=10, as N_a increases from 1× 10¹ cm^-2eV^-1 to 1 × 10¹²cm^-2 eV^-1, the transfer characteristics shift rightward, and V_TH changes from -0.67V to -0.13 V. While the subthreshold swing degrades from 63 mV/decade to 74 mV/decade. As the location of the peak concentration (E_mid) changes from the conduction band edge (E_mid=3.3eV) to the middle of the band gap (E_mid=1.7eV), the VTH shifts from -0.62 V to -0.13