TY - JOUR
T1 - Integrated Switched-Capacitor Low-Pass Filter with Combined Anti-Aliasing Decimation Filter for Low Frequencies
AU - von Grunigen, Daniel C.
AU - Sigg, Rainer
AU - Ludwig, Michael
AU - Brugger, Urs W.
AU - Moschytz, George S.
AU - Melchior, Hans
PY - 1982/12
Y1 - 1982/12
N2 - A new combined anti-aliasing decimation filter is presented which allows the implementation of a low-frequency switched-capacitor filter on a single chip. Experimental results are presented for a CMOS second-order low-pass filter with 1 dB passband ripple, a cutoff frequency of 2 Hz, and a dynamic range of 84 dB. The decimation filter converts the input clock of 16 kHz into an output clock of 250 Hz. The integrated anti-aliasing filter has a low pole frequency of about 3 kHz.
AB - A new combined anti-aliasing decimation filter is presented which allows the implementation of a low-frequency switched-capacitor filter on a single chip. Experimental results are presented for a CMOS second-order low-pass filter with 1 dB passband ripple, a cutoff frequency of 2 Hz, and a dynamic range of 84 dB. The decimation filter converts the input clock of 16 kHz into an output clock of 250 Hz. The integrated anti-aliasing filter has a low pole frequency of about 3 kHz.
UR - http://www.scopus.com/inward/record.url?scp=0020270351&partnerID=8YFLogxK
U2 - 10.1109/jssc.1982.1051856
DO - 10.1109/jssc.1982.1051856
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AN - SCOPUS:0020270351
SN - 0018-9200
VL - 17
SP - 1024
EP - 1029
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 6
ER -