Standard cell generation is an optimization problem in which we attempt to optimize its width and performance, subject to the given height of the library cells. The resulting layout is affected by three factors: image definition, transistor placement and internal routing. Extensive research has been devoted for the second factor, while only few results have been published on the others. This paper presents an integrated, systematic and practical approach to standard cell generation which addresses the above three factors. Unlike the traditional practice, the new tool served both as an image design tool as well as a cell generator. The cell image was carefully designed to enable the layout of high complexity circuits while optimizing the resulting cell area and performance. The placement problem has been decomposed into several stages in order to handle efficiently large circuits. Appropriate algorithms which take advantage of the internal structure of logical circuits and aim the mind of a layout designer are employed for each stage. The proposed generic image allows various types of wiring. Appropriate routing algorithms are driven by performance considerations and minimize the width of the final layout. The resulting image definition and the cell layout algorithms are employed in an industrial design environment and yield substantial improvements in electrical performance, area utilization and productivity.
|State||Published - 1989|
|Event||16th Conference of Electrical and Electronics Engineers in Israel, EEIS 1989 - Tel-Aviv, Israel|
Duration: 7 Mar 1989 → 9 Mar 1989
|Conference||16th Conference of Electrical and Electronics Engineers in Israel, EEIS 1989|
|Period||7/03/89 → 9/03/89|
Bibliographical notePublisher Copyright:
© 1990 IEEE.