Influence of series massive resistance on capacitance and conductance characteristics in gate-recessed nanoscale soi MOSFETs

Ultrathin body (UTB) and nanoscale body (NSB) SOI MOSFET devices, having a channel thickness (tSI) ranging from 46 nm (UTB scale) down to 1.6 nm (NSB scale), were fabricated using a selective "gate recessed" process on the same silicon wafer. The gate-to-channel capacitance (Cp) and conductance (Gp) complementary characteristics, measured for NSB devices, were found to be radically different from those measured for UTBS. Consistent Cp and Gp trends are observed by varying the frequency (f), the channel length (L), and the channel thickness (tSI). In this paper, we show that these trends can be analytically modeled by a massive series resistance depending on the gate voltage and on the channel thickness. The effects of leakage conductance and interface trap density are also modeled. This modeling approach may be useful to analyze and/or simulate electrical behavior of nanodevices in which series resistance is of a great concern.