Abstract
In this paper we examine the influence of CMOS CCII non-idealities in an IC realization of a two-integrator Biquad. We compare two CMOS-CCII realizations of the Biquad; the same basic topology of the translinear CCIIs, but the W/L ratios of their transistors are optimized differently. One CCII possesses fewer non-idealities, while the other operates at higher frequencies. It is shown how the CCII nonidealities, causing lossy integrators, are applied in the Biquad design. Realizability constraints are given. With the example of a fourth-order 1MHz/100kHz BP filter, post-layout simulations with AMS 0.35-micron technology using Cadence, show close agreement with our analysis.
Original language | English |
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Title of host publication | 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 89-92 |
Number of pages | 4 |
ISBN (Electronic) | 9781538673928 |
DOIs | |
State | Published - 2 Jul 2018 |
Event | 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 - Windsor, Canada Duration: 5 Aug 2018 → 8 Aug 2018 |
Publication series
Name | Midwest Symposium on Circuits and Systems |
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Volume | 2018-August |
ISSN (Print) | 1548-3746 |
Conference
Conference | 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 |
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Country/Territory | Canada |
City | Windsor |
Period | 5/08/18 → 8/08/18 |
Bibliographical note
Publisher Copyright:© 2018 IEEE
Funding
This work was fully supported by the Croatian Science Foundation under project (IP-2016-06-1307) "Fractional analog and mixed systems for signal processing".
Funders | Funder number |
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Hrvatska Zaklada za Znanost | IP-2016-06-1307 |
Keywords
- AMS 0.35 m
- Biquad
- Cadence
- Nonidealities
- Pspice
- Second-generation current conveyors