Improving speed and power characteristics of pulse-triggered flip-flops

Marco Lanuzza, Ramiro Taco

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper presents a simple circuital technique to design efficient pulse triggered flip-flops. The proposed approach aims at considerably alleviating the detrimental effects of current contention mechanisms, occurring at critical switching nodes during an output switching. In this way, both latency and power consumption are reduced. The proposed approach is assessed by means of simulations in 90-nm ST commercial CMOS technology. When applied to some recently proposed implicit pulse triggered flip-flop architectures, the suggested design strategy, allows speed to be improved up to 13% and power-delay-product to be lowered down to 14%. Moreover, also the process variation tolerance is considerably improved.

Original languageEnglish
Title of host publication2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings
PublisherIEEE Computer Society
ISBN (Print)9781479925070
DOIs
StatePublished - 2014
Externally publishedYes
Event2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Santiago, Chile
Duration: 25 Feb 201428 Feb 2014

Publication series

Name2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings

Conference

Conference2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014
Country/TerritoryChile
CitySantiago
Period25/02/1428/02/14

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