Improved two-step clock-feedthrough compensation technique for switched-current circuits

Markus Helfenstein; George S. Moschytz

doi:10.1109/82.686693

Improved two-step clock-feedthrough compensation technique for switched-current circuits

Markus Helfenstein
, George S. Moschytz

Swiss Federal Institute of Technology Zurich

Research output: Contribution to journal › Article › peer-review

13 Scopus citations

Abstract

A new clock-feedthrough compensation scheme for switched-current circuits is proposed. The scheme is especially suited for the design of delay lines for high-frequency operation. The circuit operates by using an improved two-step technique, in which the input is sampled in a parallel combination of a coarse and a fine memory transistor. Since both transistors are of the same type, large switching transients compared to the conventional S²I scheme can be avoided. Using the proposed circuit, the coarse memory has considerably more time to settle. Compared to the simple cell, the circuit solution requires only one extra switch and one additional clock phase.

Original language	English
Pages (from-to)	739-743
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume	45
Issue number	6
DOIs	https://doi.org/10.1109/82.686693
State	Published - 1998
Externally published	Yes

Bibliographical note

Funding Information:
Manuscript received April 29, 1996; revised May 1, 1997. This work was supported by the KWF Jessi-Project, 2302.1 Eureka EU 127. This paper was recommended by Associate Editor W. D. Grover. The authors are with the Institute of Signal and Information Processing, Swiss Federal Institute of Technology, CH-8092 Zürich, Switzerland (e-mail: [email protected]). Publisher Item Identifier S 1057-7130(98)02141-7.

Funding

Manuscript received April 29, 1996; revised May 1, 1997. This work was supported by the KWF Jessi-Project, 2302.1 Eureka EU 127. This paper was recommended by Associate Editor W. D. Grover. The authors are with the Institute of Signal and Information Processing, Swiss Federal Institute of Technology, CH-8092 Zürich, Switzerland (e-mail: [email protected]). Publisher Item Identifier S 1057-7130(98)02141-7.

Funders	Funder number
Kommission zur Förderung der wissenschaftlichen Forschung	2302.1 Eureka EU 127

Keywords

Analog sampled-data circuits
Charge injection
Sample/hold
Switched-current circuits

Access to Document

10.1109/82.686693

Cite this

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title = "Improved two-step clock-feedthrough compensation technique for switched-current circuits",

abstract = "A new clock-feedthrough compensation scheme for switched-current circuits is proposed. The scheme is especially suited for the design of delay lines for high-frequency operation. The circuit operates by using an improved two-step technique, in which the input is sampled in a parallel combination of a coarse and a fine memory transistor. Since both transistors are of the same type, large switching transients compared to the conventional S2I scheme can be avoided. Using the proposed circuit, the coarse memory has considerably more time to settle. Compared to the simple cell, the circuit solution requires only one extra switch and one additional clock phase.",

keywords = "Analog sampled-data circuits, Charge injection, Sample/hold, Switched-current circuits",

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note = "Funding Information: Manuscript received April 29, 1996; revised May 1, 1997. This work was supported by the KWF Jessi-Project, 2302.1 Eureka EU 127. This paper was recommended by Associate Editor W. D. Grover. The authors are with the Institute of Signal and Information Processing, Swiss Federal Institute of Technology, CH-8092 Z{\"u}rich, Switzerland (e-mail: [email protected]). Publisher Item Identifier S 1057-7130(98)02141-7.",

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AB - A new clock-feedthrough compensation scheme for switched-current circuits is proposed. The scheme is especially suited for the design of delay lines for high-frequency operation. The circuit operates by using an improved two-step technique, in which the input is sampled in a parallel combination of a coarse and a fine memory transistor. Since both transistors are of the same type, large switching transients compared to the conventional S2I scheme can be avoided. Using the proposed circuit, the coarse memory has considerably more time to settle. Compared to the simple cell, the circuit solution requires only one extra switch and one additional clock phase.

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Improved two-step clock-feedthrough compensation technique for switched-current circuits

Abstract

Bibliographical note

Funding

Keywords

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