Improved two-step clock-feedthrough compensation technique for switched-current circuits

Markus Helfenstein, George S. Moschytz

Research output: Contribution to journalArticlepeer-review

13 Scopus citations

Abstract

A new clock-feedthrough compensation scheme for switched-current circuits is proposed. The scheme is especially suited for the design of delay lines for high-frequency operation. The circuit operates by using an improved two-step technique, in which the input is sampled in a parallel combination of a coarse and a fine memory transistor. Since both transistors are of the same type, large switching transients compared to the conventional S2I scheme can be avoided. Using the proposed circuit, the coarse memory has considerably more time to settle. Compared to the simple cell, the circuit solution requires only one extra switch and one additional clock phase.

Original languageEnglish
Pages (from-to)739-743
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume45
Issue number6
DOIs
StatePublished - 1998
Externally publishedYes

Bibliographical note

Funding Information:
Manuscript received April 29, 1996; revised May 1, 1997. This work was supported by the KWF Jessi-Project, 2302.1 Eureka EU 127. This paper was recommended by Associate Editor W. D. Grover. The authors are with the Institute of Signal and Information Processing, Swiss Federal Institute of Technology, CH-8092 Zürich, Switzerland (e-mail: helfenst@isi.ee.ethz.ch). Publisher Item Identifier S 1057-7130(98)02141-7.

Keywords

  • Analog sampled-data circuits
  • Charge injection
  • Sample/hold
  • Switched-current circuits

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