Improved read access in GC-EDRAM memory by dual-negative word-line technique

Roman Golman, Robert Giterman, Odem Harel, Adam Teman

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Embedded memories occupy an increasingly dominant portion of the area and power budgets of modern SoCs and are also a limiting factor in VDD scaling. GC-eDRAM is a dense, low power option for embedded memory implementation, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires an additional boosted voltage supply for successful write operations. This work presents a novel technique that uses the same negative voltage applied to the write port in many GC-eDRAMs topologies to expedite the read operation and/or further increase the DRT by using it during read operations. An 8 kbit memory macro was implemented in a 28 nm FD-SOI technology, demonstrating over 20× read latency reduction, an order-of-magnitude longer DRT, and up-to 4 order-of-magnitude lower retention power consumption over a conventional 2T GC-eDRAM.

Original languageEnglish
Title of host publication2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728133201
StatePublished - 2020
Event52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online
Duration: 10 Oct 202021 Oct 2020

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2020-October
ISSN (Print)0271-4310

Conference

Conference52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
CityVirtual, Online
Period10/10/2021/10/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE

Keywords

  • Boosted voltage
  • Embedded memory
  • GC-eDRAM
  • Low Power
  • Retention time

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