Implementation of 32nm MD5 Crypto-Processor using Different Topographical Synthesis Techniques and Comparison with 500nm Node

This work focuses on several synthetizations developed in both 32nm and 500nm technologies to evaluate the performance differences of MD5 Crypto-Processor. We decided to conduct a topographical synthesis instead of a nontopographical synthesis as it takes more parameters into account to create a more accurate design. We started by comparing some basic cells like inverters and register banks to understand the main differences between the two technologies. Several approaches were considered at this point to understand how different synthetization parameters affect the chip performance and characteristics. These different approaches were focused on time, power and area, and balanced configurations of synthesis flow. Finally, after comparing the performance given by the different approaches in basic digital structures, the balanced approach was implemented in 32nm and benchmarked with the 500nm implementation. Our conclusions were consistent among the various tests conducted and by downscaling we can expect a 10x increase in the clock frequency, a 100x decrease in power consumption, and around a 300x decrease in the area while using the 32nm technology. As a result, we developed a method to fairly compare complex systems to allow a designer to consider if the benefits justify the costs for a technology change.