Abstract
A system that automates Programmable Logic Array optimization and synthesis for VLSI design is described. PLA logic is defined via a high level Hardware Definition Language. After translation to table representation comes the logic optimization phase, carried out according to a user defined optimization criterion. The geometrical optimization phase follows, supplemented by a manual interactive graphic PLA editor. The system outputs symbolic Layout of the PLA which can be translated into polygon-level layout.
| Original language | American English |
|---|---|
| Title of host publication | the 20th Design Automation Conference |
| Publisher | IEEE |
| State | Published - 1983 |