HOPLA – PLA optimization and synthesis

S. Wimer, N. Sharfman

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


A system that automates Programmable Logic Array optimization and synthesis for VLSI design is described. PLA logic is defined via a high level Hardware Definition Language. After translation to table representation comes the logic optimization phase, carried out according to a user defined optimization criterion. The geometrical optimization phase follows, supplemented by a manual interactive graphic PLA editor. The system outputs symbolic Layout of the PLA which can be translated into polygon-level layout.
Original languageAmerican English
Title of host publicationthe 20th Design Automation Conference
StatePublished - 1983

Bibliographical note

Place of conference:Miami Beach, Florida


Dive into the research topics of 'HOPLA – PLA optimization and synthesis'. Together they form a unique fingerprint.

Cite this